stepper motor controller features: ?controls bipolar and unipolar motors ? l297 operation with added functions : ?selectable torque ripple compensated phase drive ?selectable automated switching between stepping and holding torques supply current < 400ua ?half and full step modes ?normal/wave drive ?direction control ?reset input ?step control input ?enable input ?pwm chopper circuit for current control ?two over current sensor comparators with external references input ?all inputs and outputs ttl/cmos compatible (ttl for 5v operation) ? 4.75v to 7v operation (v dd ?v ss ). ? LS8397 (dip), LS8397-s (soic), LS8397-ts (tssop) ?see figure 1 april 2009 8397-042109-1 lsi/csi l si c o m p u t e r sy s t e m s , i n c . 12 3 5 w a l t w h i t m a n ro a d , m e l v ill e , n y 1 174 7 ( 631 ) 2 71 - 0 40 0 f a x ( 631 ) 2 7 1 - 0 4 0 5 LS8397 description: the LS8397 stepper motor controller generates four phase drive signal outputs for controlling two phase bipolar and four phase unipolar mo- tors. the outputs are used to drive two h-bridges for the two motor windings in the bipolar motor or the four driver transistors for the two center- tapped windings in the unipolar motor. the motor can be driven in full step mode either in normal drive (two-phase-on) or wave drive (one-phase-on) and half step mode. the LS8397 provides two inhibit outputs which are used to control the driver stages of each of the motor phases. the circuit uses step, frd/rev and half/full inputs in a translator to generate controls for the output stages. a dual pwm chopper circuit using an on-chip oscillator, latches and volt- age comparators are used to regulate the current in the motor windings. for each pair of phase driver outputs (pha, phb, and phc, phd) each pulse of the common internal oscillator sets the latch and enables the output. if the current in the motor winding causes the voltage across a sense resistor to exceed the reference voltage, vrefs, at the compara- tor inputs, the latch is reset disabling the output until the next oscillator pulse. input for a separate reference voltage vrefh is also provided for reduc- ing holding torque when the motor is not turning. when holding torque mode is enabled with a resistor-capacitor pair connected to the rc pin, the sense comparator input reference switches between vrefs and vrefh depending on whether the motor is turning or not. the separate sense reference voltages allow for conserving power when the motor is not turning. holding torque mode can be disabled by connecting the rc pin to v ss. in the half-step stepping sequence, the phase drives alternate between one-phase-on and two-phase-on in successive steps at full power thus generating substantial ripple on the output torque. an input, ct_en is provided for selecting an operational mode in which the torque ripple is corrected. in this mode the sense input reference voltage is switched to 100% and 70.7% of the applied voltages at the vrefs and vrefh in- puts in successive one-phase-on and two-phase-on conditions, respec- tively. the control input determines whether the chopper acts on the phase driver outputs or the inhibit outputs. when the phase lines are chopped, the non-active phase line of each pair (pha, phb or phc, phd) is activated rather than de- activating the active line to reduce dissipation in the load sens- ing resistor rs. refer to figure 5b for bipolar motors. if pha is high and phb is low, current flows through q1, motor wind- ing, q4 and sense resistor rs. when chopping occurs, phb is brought high and circulating current flows through q1 and d3 and not through rs resulting in less power dissipation in rs. current decay is slow using this method. when the control in- put is brought low, chopping occurs by bringing inh1 low. in this case circulating current flows through d2, motor winding and d3 and through the power supply to ground causing the current to decay rapidly. for unipolar motors, only inhibit chopping is used. refer to figure 6. when inh1 is brought low the current flowing in either half of the center tapped mo- tor winding recirculates through the diode across it. input/output description: osc input an rc input with the resistor connected to v dd and the capac- itor connected to ground determines the oscillator chopper rate. when connected as an oscillator, the oscillator output ap- pears as a negative-going pulse at the sync pin. if the oscillat- ing pin is tied to ground, the sync pin becomes an input. osc frequency, fosc = 1/0.69rc u l a3800 lsi LS8397 figure 1 3 4 5 6 24 23 22 21 20 19 7 8 9 10 18 17 16 sync v ss home phd enable reset fwd/rev osc vrefh sense1 sense2 v dd control pha phc half/full step inh2 phb inh1 pin assignment top view vrefs 12 15 13 ct_en 14 2 1 rc 11 nc
sync as an output the sync can be used to drive sync pins of other LS8397 s. this eliminates the need for rc components for any other LS8397 controllers used in the system. as an input the sync can be driven by the LS8397 that has the rc oscillator components or by any other system external clock. pha/phb/phc/phd phase drive output signals for power stages. in a bipolar motor pha and phb are used for one h-bridge while phc and phd are used for the other. inh1/inh2 outputs these outputs are active low inhibit controls for motor drive outputs. inh1 controls driver stage using pha and phb sig- nals while inh2 control driver stage using phc and phd sig- nals. when the control input is low, these outputs are chopped using the internal oscillator for current regulating. control input when high, the phase outputs, pha, phb, phc and phd are chopped. when low, inh1 and inh2 are chopped. normally, inhibit outputs are chopped. phase chopping might be used with a bipolar motor that does not store much energy to pre- vent fast current decay and a low useful torque. enable input when enable input is low, inh1, inh2, pha, phb, phc and phd are brought low. home output an open drain output that indicates when the LS8397 is in its initial state with pha, phb, phc, phd = logic states 0101 re- spectively. refer to figure 4. in the active state the open drain device is off. step input an active low pulse on this input causes the motor to advance one step. the step occurs on the rising edge of the step signal. frd/rev input a logic 1 on this input causes the motor to advance through the stepping sequence of fig. 4. a logic 0 on this input cause the motor to reverse the sequence. reset input an active low on this input cause the motor to be restored to the home position (0101). half/full input when high, half-step operation is selected. when low, full-step operation is selected. the one-phase-on full step is selected by selecting full when the stepping sequence is at an even state. the two-phase-on full step operation is selected when the stepping sequence is at an odd state. refer to figure 4. sense1/ sense2 inputs inputs for load current sense voltages from power stages using pha and phb drive signals or phc and phd drive signals, respectively. when holding-torque mode is enabled, the motor torque is switched to stepping torque at a step command followed by holding torque after a programmable delay. the stepping torque is controlled by the reference voltage vrefs input and the hold- ing torque is controlled by the voltage at the vrefh input. the delay is controlled by a resistor-capacitor pair connected to the rc pin. when the holding-torque mode is disabled, the motor torque re- mains in the stepping torque mode all the time controlled by the vrefs voltage. rc input/output a resistor-capacitor pair connected to this pin starts a time-out delay at every step command. at the start of the delay, the ref- erence voltage at the vrefs pin is switched in for the sense comparators to produce higher stepping torque. at the end of the time-out, the reference voltage at the vrefh pin is switched in for the sense comparators to produce the lower holding torque, reducing power dissipation while the motor is stationary. the delay is given by tds = 1.4rc if tied low, holding torque mode is disabled and stepping torque is produced in both dynamic and static states by using the vrefs reference voltage. vrefs input input for the sense comparator reference voltage for produc- ing stepping torque. vrefh input input for the sense comparator reference voltage for produc- ing holding torque. ct_en input input for selecting/deselecting compensated torque-ripple mode. the step sequence in the half-step mode alternates be- tween one-phase-on and two-phase-on states resulting in torque ripple during the stepping sequence. in the compensat- ed-torque mode, the ripple is eliminated by equalizing the torques for the alternate states. this is done by alternately switching the sense reference voltages between 100% and 70.7% in alternate cycles. the ct_en input is relevant only in the half-step mode, since the alternating one-step-on and two-step-on sequence does not exist in the full-step mode. this input has an internal pull-up. 8397-011409-2
absolute maximum ratings symbol parameter value unit v s supply voltage 10 v v i input signals 7 v t stg , t j storage and junction temperatures -40 to +150 ?c electrical characteristics: (refer to block diagram, figure 2, and timing diagram, figure 3) t a = +25?c, v dd = +5v unless otherwise specified. parameter symbol minimum typical maximum unit condition ( pin 15 ) supply voltage v dd 4.75 - 7 v - quiescent supply current i dd - 300 400 ua outputs floating ( pins 13, 14, 21, 22, 23 and 24 ) input voltage low v il - - 0.75 v - input voltage high v ih 2 - - v - ( pins 14, 21, 22, 23, 29 ) input current i ih, i il - - 50 na v i = v il or v ih input current ( pin 13 ) i il - - 50 na v i = 0 i ih - - 50 na v i = v dd ( pin 10 ) enable input voltage low v enl - - 1.3 v - enable input voltage high v enh 2 - - v - enable input current i en - - 50 na v en = v enl enable input current i en - - 50 na v en = v enh ( pins 4, 6, 7, 9 ) phase output voltage low v ol - - 0.5 v i o = -10ma phase output voltage high v oh 4.0 - - v i o = 5ma ( pins 5, 8 ) inhibit output voltage low v inhl - - 0.5 v i o = -10ma inhibit output voltage high v inhh 4.0 - - v i o = 5ma leakage current ( pin 3 ) i leak - - 1 ua v ce = 7v saturation voltage ( pin 3 ) v sat - - 0.4 v i = 5ma ( pins 13, 14, 15 ) comparators offset voltage v off - 5 - mv v ref = 1v comparator bias current i o 100 - 10 ua - ( pins 18, 19 ) input reference voltages vrefs, vrefh 0 - 3 v - input currents irefs, irefh - - 8 ua vrefs, vrefh = 3v ( pin 11 ) rc input low v rcl 0 - 2.5 v - rc input high v rch 3.5 - - v - external resistor at rc r 10 - no limit k w - step pulse width t stp 0.5 - - us - set up time t s 1 - - us - hold time t h 4 - - us - reset time t r 1 - - us - reset to step delay t rstp 1 - - us - ( pin 20 ) oscillator: sawtooth low v sol - 2.1 - v - sawtooth high v soh - 3.65 - v - 8397-040709-3
figure 3. input timing diagram 8397-040709-4
1 2 3 4 5 6 7 8 0101 1001 0001 1000 1010 0010 0110 0100 home 1 2 3 4 5 6 7 8 1000 0010 0100 0001 step 1 3 5 7 1 3 5 7 1 3 5 7 a b c
figure 5a. typical application schematic for a two - phase bipolar motor using a single motor driver ic figure 5b. one half of l298 drive stage 8397-111308-6 v m pha phb inh1 q1 q2 q3 q4 d1 d3 d4d2 r s sense1 17 18 2 20 10 21 22 24 15 23 7 4 8 5 16 11 7 10 9 4 2 3 13 14 1 15 8 mcu LS8397 l298 +5v v m reset enable stepper motor windings pha phb phc phd sense1 inh1 inh2 step frd/rev v dd v ss sense2 9 12 6 inh1 inh2 pha phb phc phd 5 6 r s r s out1 out2 out3 out4 v dd vs half/full control sensea v ss senseb see note note: the sense resistors on l298 should be chosen so that i max = v r s / r s , where i max is the maximum motor winding current. 22k 3.3nf v rs v rh vrefs vrefh 19 14 +5v osc rc 11 r c ct_en 13
8397-040609-7 figure 6. typical application schematic for a four - phase unipolar motor using discrete mosfet transistors note: q1, q2, q3, q4 are mosfet power transistors suitable for 5v gate drive typical p/ns = irlz44n and irf3708 20 10 21 15 23 16 mcu LS8397 +5v enable step frd/rev v dd 2 v ss reset osc 17 18 sense2 4 5 pha phb inh1 6 sense1 8 9 7 phc phd inh2 v m v m 1 2 3 74hc08 74hc08 4 5 6 9 10 12 13 8 q1 q2 q3 q4 11 half/full control 24 22 +5v r c 11 rc ct_en r s = v rs i max 13 vrefh 14 v rh vrefs 19 v rs 3.3nf 22k r s = v rs i max
figure 7. synchronizing multiple LS8397s 8397-041309-8 22k 3300pf +v osc sync sync sync osc osc LS8397 20 20 20 1 1 1 LS8397 LS8397 the information included herein is believed to be accurate and reliable. however, lsi computer systems, inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use.
|
